Porting Arducam Mega to Xilinx zc7020

  1. Where did you get the camera module(s)?
  2. Model number of the product(s)?

X003Z1MKQ9 (Arducam Mega 5MP 10th anniv edition)

  1. What hardware/platform were you working on?

zynq 7z020/petalinux using spidev/mraa

  1. Instructions you have followed. (link/manual/etc.)

Code from the Arducam Mega repo on github and the mega spi camera series application node.

  1. Problems you were having?

I am looking at the code which uses registers that are not defined in the application note. Any searching I do for these descriptions turns up previous register maps that don’t correspond to the code,
although there are analogs at other addresses (for example, the trigger loop is related to FIFO done).

My specific problem is that using the resolution QVGA (320x240), my FIFO size is 603560. I would have expected it to be somewhere around 76800. However, its difficult to debug without an accurate register map.

  1. The dmesg log from your hardware?

I have hooked up the SPI bus analyzer and it seems that the transactions are working correctly.

  1. Troubleshooting attempts you’ve made?

In debugging this, I have verified that I can read the camera id, version, and so forth, including updating the test register. I have also verified the SPI transactions via logic analyzer.

  1. What help do you need?
    An accurate register map.

Please check the doc below: