Now I’m trying connect my own FPGA sensor board to UC-391 Rev.D Arducam USB Shield.
Connection between FPGA to UC-391 are simple as like below.
HSYNC - 640x400 pixel resolution
VSYNC - 35fps
PCLK - 12.5MHz (FPGA main clock is 50MHz and this clock is divided by 4)
and 8bit data line
FPGA main code
assign HS = ~ (xc > 640 |(y > 510) | (y < 30));
assign VS = ~ ((y > 510) | (y < 30));
assign x = ((xc < 192)?0:(xc - 192));
always @(posedge CLK)
begin
PCLK <= ~PCLK;
end
always @(posedge PCLK)
begin
P2CLK <= ~P2CLK;
end
always @(negedge P2CLK)
begin
if (xc == 734)
begin
xc <= 0;
y <= y + 1;
end
else begin
xc <= xc + 1;
end
if (y == 522)
begin
y <= 0;
end
end
endmodule
Unfortunately, USBTest program always showing the “Bad frame received”.
Question) Is it possible to customized interface like me?
fpga4u
2
@KC Chang
In order to implement customize sensor input, you have to modify the config file for your particular sensor or FPGA simulated input.
Bad frame received means the received image data size is not the same as expected image size defined in the config file.
You can also use “Force Display” check box to force preview the captured video data even if it is not compliance to the settings.
@Lee Jackson
Thanks for your comment!
I have adjust the FPGA timing based on OV7675 VGA mode and have a good result.
Thanks a lot!
module vga(
input CLK,
output PCLK,
output HS, VS,
output [9:0] x,
output reg [9:0] y
);
reg [9:0] xc;
reg [3:0] counter;
// VSYNC = 3T(H) + 507T(L)
// HSTART = 17T
// HREF = 640(H)+144(L)
assign HS = ~(xc > 639 | (y < 17) | (y>496));
assign VS = (y < 3) ? 0 : 1;
assign x = (xc < 200)? 0 : 1;
assign PCLK = counter[3] ? 1 : 0;
always @(posedge CLK)
begin
counter <= counter + 1;
end
always @(negedge PCLK)
begin
if (xc == 783)
begin
xc <= 0;
y <= y + 1;
end
else begin
xc <= xc + 1;
end
if (y == 510)
begin
y <= 0;
end
end
endmodule